Maxwell Lite A Little Too Light?

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Green Eyes’ Acolytes Vs. The World

Nvidia Minion:  The 970 has 4GB of memory just as advertised but we decided to separate the last 0.5 gigabytes from a central reserve of 3.5GB.

The Angry:  And why pray did you do that, Giant Green Eyes?

Nvidia Minion:  Please be merciful, I’m not Green Eyes, I’m but a humble minion who preaches on his behalf, can’t you tell by my thin, reedy voice.

The Wronged:  Just answer the question.

Nvidia Minion:  It was part of our new binning method to improve yield rates, you know, like how we disabled three streaming processors on your GPU and left them active on the 980.

The Outraged:  What has that got to do with the memory?

Nvidia Minion:  Listen, the manufacturing process for our ingeniously detailed designs is still comparatively cumbersome.  But our lord and master is continually establishing more refined and efficient techniques to disable non-essential elements on chips that don’t qualify for our flagship products .  That way we preserve as much performance as possible for you, the customer.  This is one such example.

We were able to isolate and disable a section of level two cache, 256k, exactly one eighth of the Maxwell’s total, along with 8 render output processors, but leave the adjoining memory controller active and ensure all four gigs of RAM remained accessible.

The Seething:  I see, so not only do we have 512 megs of terminally crippled memory, we’ve also got less ROPs and cache than we were led to believe.

Nvidia Minion:  Well, had we not done this, we’d have had to fuse off two memory controllers, 16 ROPs, half a meg of cache and render a whole gig of RAM completely redundant.  In other words, sell you a card with 3 gigs instead of 4, but we didn’t think you’d want  that.

The Furious:  Don’t be impertinent. What you SOLD us wasn’t what you promised.   I can’t believe you’re actually trying to make such cynical and greedy marketing sound like some masterfully conceived and beneficial production decision.  One more time, why did you split up the memory?

Nvidia Minion:  The memory controller communicating with that last half gig doesn’t have its own portion of cache, because we disabled it.  So in order for its data to reach the crossbar, the fat bit in the middle, it has to be delivered via the cache and crossbar port connected to its neighbouring controller.  Remarkably, it can, the other controller is an obliging chap and more than happy to share his port and cache, so the two of them hook up through what we call a “buddy interface”, isn’t that cute?

The Enraged:  Cute?  As in shrewd?  Absolutely!

Nvidia Minion:  The one, very minor drawback is that this poor deprived controller can’t work as quickly as the other seven by virtue of having to share his partner’s cache.  In fact he’s only one seventh as efficient,  so we separated the RAM he talks to from the main section that those other seven controllers interact with and gave the latter priority over the former.

The Exploited:  Please, that’s enough personifying.  We’re not in primary school.  Don’t try to turn this into a sugary syrupy piece of contemporary children’s fiction in the hope of persuading us that you have a heart, or melting ours.  Just get on with it.

Nvidia Minion:  Don’t worry, we won’t melt anything, that’s AMD’s job.  Anyway, segmenting and categorizing  the memory means applications that require less than 3.5 gigs, the vast majority, will only ever occupy the larger and faster section, whilst those that need more, very few, will be granted use of that last half gig.  If we’d left the memory undivided, the entire pool’s bandwidth would have been relegated to 50% of its capacity.

The Appalled:  Why?

Nvidia Minion:  Because those last two memory controllers are sharing a crossbar port,  remember? The second port was sacrificed along with the ROPs and cache.  But each controller still has to satisfy the orders assigned by the tiny  1kb matchstick man who sprints along the memory bus, so that the SMMs on the other side of the crossbar can access  and utilize the VRAM.

The Disgruntled:  NO MORE PERSONIFYING.

Nvidia Minion:  Beg your pardon. So  If the RAM weren’t partitioned, the memory interface would attempt to operate as though the eighth port still existed, placing the seventh port under twice as much load as usual.  Meanwhile, its two associated controllers, our odd couple, budded up or otherwise, would effectively be fulfilling RAM requests at half the rate of the other six, all of which still have one port a piece and would hence, always be forced to wait for these last two to catch up.

Let’s try an analogy.  Imagine a RAID 1+0 array of hard disks made up of eight drives.  Seven of the drives are identical but the eighth is a mismatch and slower than the others.  We arrange these drives in an array consisting of four RAID 1 pairings, which are then linked together, or “striped” as one big RAID 0 array.  As only seven of the comprising drives match, three pairings would be able to operate at their maximum speed, but the fourth would be encumbered by the runt drive.

As a RAID 0 array depends of every disk making simultaneous writes, this would result in the three healthy pairings or “mirrors” being impeded by the fourth, thereby compromising the throughput of the entire array.

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