“The Sky’s the Limit…Are You So Sure?”

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A titillating total of 26 high speed I/O ports served the chipset exclusively, 20 of which were designated as tertiary generation PCI Express lanes, with all linked directly to a ground breaking controller hub, aptly entitled “sunny point”.

The basic configuration allocated 6 fixed lanes to USB 3.0 ports, thereafter, a broad range of resource profiles were assignable at the manufacturer’s discretion, with ample accommodation for a variety of contemporary supplements including USB 3.1, which most elected to implement via Asmedia’s ASM1142 controller, a two lane solution reaching the interface’s maximum of 10 gigabits per second, the same as Sata Express.

One alternative was Intel’s “Alpine ridge”, a propriety solution initially in short supply and readily employed by Gigabyte, who aggressively marketed it as a higher quality and more versatile method of integration.  The Chip provided a bandwidth ceiling of 40 gigabits per second and transmitted Thunderbolt 3, USB 3.1, Displayport 1.2 and 10 Gig Ethernet over USB’s reversible “type” C” connector.

The remaining 18 lanes could then be apportioned to such bare essentials as SATA and integrated Ethernet controllers, as well as a trio of “PCIe” storage peripherals,  4 channels a piece and each assignable as a RAID device.  For the first time ever, this allowed solidified stalwarts to create boot-able arrays incorporating SATA Express and M.2 drives at BIOS level and in the case of certain motherboards, even facilitated combining conventional solid state disks with those manifest in card form.

Following  a gruelling session of murderous bench testing, the maestros at PC Perspective were able to marry a PCI based Intel 750 with its asymmetrical twin connected via Asus’s Hyper Kit and experience transfer rates topping 3 gigabytes per second, so fast that they approached the capacity of the chip set, triggering an deluge of excited enquiries that caused the team’s resident memory guru to go Woohhhaaaaa!

Skylake’s sensational PCH communicated with the CPU through a quad channel “Direct Media Interface”, also underpinned by PCI’s third revision and twice as capacious as that of any ancestor’s, whilst the lane tally tethering the processor to the PCI subsystem remained at 16.  This, along with the omission of Native USB 3.1 and the devolved HD 530 GPU were the only shortfalls of arguably the most lavish middle tier chip set ever woven by Intel’s wizardry.

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